A 0.2-to-2.0GHz 65nm CMOS Receiver without LNA achieving >11dBm IIP3 and <6.5 dB NF

Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited [1]. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core [2,3] for low conversion loss and low noise folding it is shown that it is possible to realize IIP3≫11dBm and NF≪6.5dB, i.e. a remarkably high SFDR≫79dB in 1MHz bandwidth over a decade of RF frequencies

Advances in silicon phased-array receiver IC's

Phased-Arrays are increasingly used, and require Silicon implementations to result in affordable multi-beam systems. In this paper, CMOS implementations of two novel analogue beamforming multi-channel receivers will be presented. A narrow-band highly linear system exploiting switches and capacitors in advanced CMOS is presented, implementing a fully passive switched capacitor vector modulator exploiting a zero-IF I/Q mixer: This technique is not applicable to very wideband phased-array receivers. These systems require true-time delay beamforming, which is implemented in the second CMOS implementation. An innovative gm-RC implementation of a true-time delay cell is exploited in a four-channel beamforming receiver with more than L.5 GHz bandwidth, in a standard 0.13 um CMOS process. Professional phased-arrays can often not live with the dynamic range limitations imposed by these implementations. To that end a SiGe implementation of an integrated receiver was realized targeting a digital beamforming phased-array. Dynamic range and flexibility of use were the main driving factors. Alltogether, these results show large progress with respect to the feasibility of Silicon-based phased-array front-end implementation for commercial as well as professional phased-arrays. © 2012 IEEE

Switched-RC beamforming receivers in advanced CMOS : theory and design

In consumer electronic devices, analog radio transmitters and receivers provide the wireless links between devices. These radios are mostly omnidirectional, i.e. transmitters send their energy in all directions and receivers listen to signals from all directions. As a result, interference between devices and services is becoming an increasing problem as more wireless connectivity is added. In order to transmit and receive directional 'beams', it is necessary to add multiple antennas to the radios and to control their precise relative delays. For the implementation of such a system in consumer electronics, it is required to add additional time delay and/or phase shift circuits to the existing radio architectures. These circuits are challenging to fabricate in mainstream CMOS technology and must be very linear, as they are subject to the unfiltered interferers. A rigorous analysis reveals that a switched-resistor-capacitor current loop can be the building block for high linearity circuits. The transfer function and noise contribution of this loop depend on the ratio between the RC time constant and the switch-on time. Two distinctive operating regions are identified, one with low noise properties for mixer applications, and one with high bandwidth properties for sampling applications. Three designs are implemented during this research project. The first demonstrates a high linearity downconverter with a mixer-first topology, based on mixing region switched-RC loops. The second adds beamforming capabilities with a discrete-time vector-modulator phase shifter, based on sampling region switched-RC loops. The third design evolves the previous designs into an all-passive topology where the impedance matching for the mixer is achieved by the charge dissipation in the phase shifter. This design stands out in linearity performance and is easily portable to future CMOS technologies

Effects of Thermal Effluents from the Second Nuclear Power Plant on Periphytonin Northern Taiwan, with Notes on Phytoplankton

興建於沿岸之電廠所排放之溫排水會使出水口附近局部沿岸海域水溫提升，而溫排水中所添加之氯化物亦可能使沿岸生態系受到影響。本實驗之目的主要針對台灣北部核能二廠溫排水對附近沿岸海域的浮游藻類和礁岩附生藻類之影響為研究重點，以光合作用溶氧法培養、測量並比較生產力與豐度是否於出、入水口之間存在差異性，以及此差異是否因季節改變而有變化，藉以評估溫排水對於出水口與入水口藻類群聚的影響。本實驗將2003年的研究結果與過去林等(2001-2002)的調查監測資料整合，探討三年間出、入水口間基礎生產者(藻類)各生物參數的時空動態變化情形。附生藻類生產力的結果顯示，出、入水口間單位葉綠素a生產力的最大值(PB Max)的最大差異出現在夏季，而且在生長季節的春、秋季，入水口單位葉綠素a生產力的最大值(PBMax)亦顯著高於出水口。另一方面，入水口的單位葉綠素a生產力的最大值(PBMax)會隨溫度上生而升高，但出水口卻反而隨溫度升高而降低，可能是因為出水口的高溫已對附生藻類的生產力造成負面影響。若從單位葉綠素a生物量的變化上來看，雖然出水口的附生藻類在夏季的生產力較低，但單位葉綠素a生物量卻是一年中累積最多的時候，推測因為出水口的高溫使其掠食者較少的緣故。由聚類分析(cluster analysis)與多尺度空間排序(MDS)的結果明顯分出出入水口之間是有顯著差異的。大型附生藻類中的腸石髮( Enteromorpha intestinalis )只於出水口出現，並且於高溫的夏季累積最多，是已適應於高溫中生長的大型藻類，與台灣南部墾丁潮間帶有相類似的情形。而在春、秋季生產力旺盛時，底棲微藻是出水口附生藻類群聚生產力的主要的貢獻者，其優勢藻屬分別為菱形藻屬( Nitzschia )、舟形藻屬( Navicula )與曲殼藻屬( Achnanthes )。入水口附生藻類群聚不同於出水口處除了藻屬(種)的不同之外，主要的生產力貢獻者為大型附生藻類，但附生微藻的種類卻高於出水口。在浮游藻類的部分，單位葉綠素a生物量顯著高於出水口約50％。若由出水口與入水口兩測站單位葉綠素a生物量差異之季節性變化趨勢來看，夏季為入水口浮游藻類大量生長的季節，但出水口浮游藻類較無明顯季節性變化。此外，由浮游藻類生產力的結果發現，出水口生產力於夏季高溫時達到最高，可見溫度應不是主要影響浮游藻類的主要因素。2004年7月的實驗結果顯示，核能二場的餘氯濃度對附生藻類並無顯著影響，可見應是溫度影響出水口附生藻類光合作用，使PBMax隨溫度升高而有降低的趨勢。同時，高溫與不同濃度氯的添加實驗顯示，夏季的浮游藻類確實會因高溫(40℃)抑制其生產力，但氯的影響更為顯著，當氯的濃度達0.2 ppm，就幾乎完全抑制浮游藻類的生產力。而2001年至2003年間出水口浮游藻類生物量被抑制而無明顯季節性變化應是核能二廠持續的餘氯濃度(0.1 ppm)所致。整體而言，出、入水口間的附生藻類群聚組成因溫度而不同，出水口藻類為較耐高溫藻種。而高溫環境會降低附生藻類生產力，但夏季出水口的高溫使藻食性魚類數量減少反而使其生物量累積。此外，夏季的高溫(40℃)致浮游藻類生產力降低至原來的1/12，但是當餘氯濃度超過0.1 ppm時，浮游藻類生產力幾乎降為零。可見餘氯相較於高溫而言，對浮游藻類的負面影響是更大的。目 錄 摘要…………………………………………………………………………………………..i 目錄……………………………………………………………………...………………….iii 表目錄…………………………………………………………...….……..………………..v 圖目錄………………………………………………………………….............................vi 第一章、前言…………………………………………………………………………….1 第二章、、材料與方法…………………………………………………………………..8 一、採樣地點…………………………………………………………………………8 二、採樣實驗時間……………………………………………………………………8 三、環境因子……………………………………………………………………….10 四、基礎生產力測定之基本原理…………………………………………………..10 (一)生產力基本原理…………………………………………………...………..10 (二)基礎生產力之測定………………………………………………………….15 五、基礎生產者葉綠素a之測定………………………………………………….15 (一)浮游藻類…………………………………………………………………….16 (二)附生藻類…………………………………………………………………….17 六、附生藻類群聚中種類之鑑定與比例之估算…………………………………..17 (一)藻種鑑定…………………………………………………………………….17 (二)附生藻類群聚組成………………………………………………………….17 七、光合作用與光強度關係分析方法……………………………………………..20 八、不同濃度氯的添加實驗(2004年7月資料)………………………………….23 (一)浮游藻類-放射性碳十四法…………………………………………………23 (二)附生藻類…………………………………………………………………….23 九、浮游藻類於高溫與餘氯處理實驗(2004年7月資料)………………………24 第三章、結果…………………………………………………………………………….25 一、光度變化………………………………………………………………………..25 二、環境因子………………………………………………………………………..25 三、附生藻類生物參數…………………………………………………………….31 四、附生藻類生產力與光合作用參數……………………………………………..38 五、不同濃度氯對附生藻類生產力之影響……………………………………….43 六、浮游藻類單位葉綠素a的含量……………………………………………….44 七、 浮游藻類生產力與光合作用參數……………………………......................44 八、浮游藻類於不同濃度氯與溫度處理之反應………………………………….47 第四章、討論…………………………………………………………………………….49 一、附生藻類………………………………………………………………………..49 二、浮游藻類………………………………………………………… …………….51 第五章、參考文獻………………………………………………………………………5

A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution

Phased-array receivers provide two major benefits over single-antenna receivers [1]. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking [2], phase selection [3] and vector modulation [1,4,5,6]. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge-redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights. © 2011 IEEE

A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS

Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity

Spatial Interferer Rejection in a 4-Element Beamforming Receiver Frontend with a Switched-Capacitor Vector Modulator

A 1-4GHz 4-element phased array receiver frontend demonstrates spatial interferer rejection using null steering. Element phase and amplitude control are performed by a switchedcapacitor vector modulator with integrated downconversion, utilizing a rational sine/cosine approximation. The 65nm CMOS receiver achieves more than 20dB of spatial interferer rejection up to an angular separation of 15°

A 0.2-to-2.0GHz 65nm CMOS Receiver without LNA achieving >11dBm IIP3 and

Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited [1]. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core [2,3] for low conversion loss and low noise folding it is shown that it is possible to realize IIP3≫11dBm and NF≪6.5dB, i.e. a remarkably high SFDR≫79dB in 1MHz bandwidth over a decade of RF frequencies

A Beamformer with constant-gm vector modulators and its spatial intermodulation distortion

Spatial interference rejection in analog adaptive beamforming receivers can improve the distortion performance of the circuits following the beamforming network, but is susceptible to the non-linearity of the beamforming network itself. This paper presents an analysis of intermodulation product cancellation in analog active phased array receivers and verifies the distortion improvement in a 4-element adaptive beamforming receiver for low power applications in the 1.0 to 2.5 GHz frequency band. In this architecture, a constant-Gm vector modulator is proposed which produces an accurate equidistance square constellation, leading to a sliced frontend design that is duplicated for each antenna element. By moving the transconductances to RF, a four-fold reduction in power is achieved, while simultaneously providing input impedance matching. The 65-nm implementation consumes between 6.5 and 9 mW per antenna element, and shows a +1 to +20 dBm in-band, out-of-beam IIP3 due to intermodulation distortion reduction